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Update README.md and add tests/README.md
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‎README.md

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<img src="images/uart01_chip.svg" title="UART01-V Chip in Verilog" align="right" width="6.3%">
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<br />
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<br />
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# uart-verilog
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8 bit UART includes tests, documentation, timing diagrams
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8 bit UART with tests, documentation, timing diagrams
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&ensp;&ensp;For simulation and Electronic Design Automation
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#### Parameters
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The baud rate is parametrized; e.g.:
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Selected rates, e.g.:
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```
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CLOCK_RATE = 12000000
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```
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```
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BAUD_RATE = 115200
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```
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Mode 8-N-1 or 8-N-2 (8 bits data, no parity, 1 or 2 stop bits). The default 2 stop bits:
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```
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TURBO_FRAMES = 0
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```
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&ensp;&ensp;trades off maximum bandwidth against more reliable communication
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![Multiple module design of the UART](images/Uart3ChipScreenShot.png "Hierarchy of the design showing the Verilog modules: Transmitter, Receiver, Baud clock generator")
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#### Test benches
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Functional.
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&ensp;&ensp;Direct to [the tests](tests/)
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Some text.
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#### Running the tests on your machine
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The test benches can be run using the open source simulator Icarus Verilog: [Installation][link-iverilogi], [Getting Started][link-iverilogs].
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With it installed, you can run a command like the following that specifies the required input files and one output file (.vvp):
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> iverilog -g2012 -I.. -osimout.vvp -D"DUMP_FILE_NAME=\"1.vcd\"" 1.v
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&ensp;&ensp;(This is run in the "tests" directory, and ".." thus references the device .v files or .vh files at root level.)
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It then requires a second step: Run the Icarus Verilog simulator/runtime to store all signal and timing data to a .vcd file (viewable signal trace):
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> vvp simout.vvp
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I combine these:
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> iverilog -g2012 -I.. -osimout.vvp -D"DUMP_FILE_NAME=\"1.vcd\"" 1.v && timeout 1 >NUL && vvp simout.vvp
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GTKWave viewer is used to view the trace (waveforms): [Installation][link-gtkwavei], [Getting Started][link-gtkwaves].
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With GTKWave installed, just click on the .vcd file. However, to persist the view (the duration window, amount of zoom and the particular signals) that you want to see for that test bench, save it as a .gtkw file. The .gtkw file persists and is a consistent view, whereas .vcd, the data, can be regenerated at will. Thus runs can be compared. (If you haven't changed the HDL code, the runs will come out identical.)
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<img src="tests/images/13.png" title="Simulation waveform" width="50%">
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#### Topics: Device and circuit simulation
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#### Related open source technology for device and circuit simulation:
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- [HDLs][link-web-hdls] · Hardware Description Languages
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- [EDA][link-web-eda] · Electronic Design Automation
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- [FPGAs][link-web-fpgas] · Field-Programmable Gate Arrays
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#### Related open source technology
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[IceChips][link-icechips] devices from 7400 TTL family
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[Icestudio][link-icestudio] and Apio built on top of IceStorm, Yosys, nextpnr
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[Yosys][link-yosys] synthesis by Claire Wolf
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[Icarus Verilog][link-iverilog] simulator by Stephen Williams
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[GTKWave][link-gtkwavei] for viewing waveforms
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## <!-- -->
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Mode 8-N-1 or 8-N-2 is parametrized. The designations mean: 8 bits data, no parity, 1 stop bit or 2 stop bits.
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© 2022-2023 Tim Rudy
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© 2022 Tim Rudy
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[link-icechips]: https://github.com/TimRudy/ice-chips-verilog
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[link-icestudio]: https://icestudio.io
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[link-web-hdls]: https://www.google.com/search?q=Hardware+Description+Languages
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[link-web-eda]: https://www.google.com/search?q=Electronic+Design+Automation
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[link-web-fpgas]: https://www.google.com/search?q=Field-Programmable+Gate+Arrays
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[link-yosys]: https://github.com/YosysHQ/yosys
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[link-iverilog]: http://iverilog.icarus.com
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[link-iverilogi]: https://steveicarus.github.io/iverilog/usage/installation.html
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[link-iverilogs]: https://steveicarus.github.io/iverilog/usage/getting_started.html
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[link-gtkwavei]: http://gtkwave.sourceforge.net
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[link-gtkwaves]: https://gtkwave.sourceforge.net/gtkwave.pdf

‎Uart8Receiver.v

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@@ -260,8 +260,8 @@ always @(posedge clk) begin
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sample_count <= sample_count + 4'b1;
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if (!err && !in_sample || &sample_count) begin
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// check if this is the change to a start signal -
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// in_sample has met the min high hold time
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// any time it drops to low in this state
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// note that in this state, in_sample has met the min high
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// hold time any time it drops to low
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// (also in these cases, namely !{err} or tick 15 special case,
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// signaling of {done} is in progress)
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if (&sample_count) begin // reached 15, last tick, and no error
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state <= `IDLE;
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end
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end else if (&sample_count[3:1]) begin // reached 14 -
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// additional tick 15 comes from transitting the READY state
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// additional tick 15 comes from transiting the READY state
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// to get to the RESET state
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if (err || !in_sample) begin
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state <= `RESET;

‎ice/UART-RX.ice

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‎ice/UART.ice

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‎images/ReceiverScreenShot.png

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‎images/Uart3ChipScreenShot.png

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‎tests/12.v

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for (t = 0; t < ENABLED_BAUD_CLOCK_STEPS; t++) begin
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#1000
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case (t)
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4: begin
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$display("%7.2fms | tx start: %d", $realtime/10000, txStart_1);
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$display("%7.2fms | rx done: %d", $realtime/10000, rxDone_2);
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$display("%7.2fms | rx data: %8b", $realtime/10000, rxByte_2);
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end
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5: begin
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txStart_1 = 1'b0;
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$display("%7.2fms | tx start: %d", $realtime/10000, txStart_1);
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$display("%7.2fms | rx done: %d", $realtime/10000, rxDone_2);
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$display("%7.2fms | rx data: %8b", $realtime/10000, rxByte_2);

‎tests/1a.gtkw

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[*]
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[*] GTKWave Analyzer v3.3.81 (w)1999-2017 BSI
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[*] Thu Feb 09 02:05:26 2023
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[*]
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[dumpfile] "1a.vcd"
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[dumpfile_mtime] "Thu Feb 09 02:04:09 2023"
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[dumpfile_size] 1227861
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[savefile] "1a.gtkw"
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[timestart] 0
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[size] 1536 937
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[pos] -9 -9
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*-18.545267 1555000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] test.
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[treeopen] test.uart1.
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[sst_width] 197
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[signals_width] 210
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[sst_expanded] 1
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[sst_vpaned_height] 482
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@22
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test.uart1.txInst.in_data[7:0]
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@28
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test.uart1.txClk
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test.uart1.txEn
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test.uart1.txStart
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test.uart1.txBusy
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test.uart1.txDone
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test.uart1.txInst.bit_index[2:0]
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test.uart1.txInst.state[2:0]
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test.uart1.txInst.out
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test.uart1.rxClk
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test.uart1.rxEn
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test.uart1.rxBusy
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test.uart1.rxDone
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test.uart1.rxErr
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test.uart1.rxInst.in
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test.uart1.rxInst.in_sample
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test.uart1.rxInst.state[2:0]
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test.uart1.rxInst.bit_index[2:0]
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@22
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test.uart1.rxInst.received_data[7:0]
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test.uart1.rxInst.out[7:0]
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[pattern_trace] 1
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[pattern_trace] 0

‎tests/1a.v

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`timescale 100ns/1ns
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`default_nettype none
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`include "Uart8.v"
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module test;
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localparam CLOCK_FREQ = 12000000; // Alhambra board
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localparam SIM_STEP_FREQ = 1 / 0.0000001 / 2; // this sim timescale 100ns
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// for the simulation timeline:
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// ratio SIM_STEP_FREQ MHz / CLOCK_FREQ MHz gives the output waveform in proper time
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// (*but note all clocks and the timeline are approximate due to rounding)
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localparam SIM_TIMESTEP_FACTOR = SIM_STEP_FREQ / CLOCK_FREQ;
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localparam ENABLED_BAUD_CLOCK_STEPS = 17;
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reg clk;
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reg en_1;
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reg txStart_1;
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wire txBusy_1;
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wire rxBusy_1;
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wire txDone_1;
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wire rxDone_1;
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wire rxErr_1;
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reg [7:0] txByte_1;
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wire [7:0] rxByte_1;
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wire bus_wire;
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Uart8 #(.CLOCK_RATE(CLOCK_FREQ)) uart1(
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.clk(clk),
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// rx interface
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.rxEn(en_1),
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.rx(bus_wire),
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.rxBusy(rxBusy_1),
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.rxDone(rxDone_1),
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.rxErr(rxErr_1),
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.out(rxByte_1),
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// tx interface
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.txEn(en_1),
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.txStart(txStart_1),
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.in(txByte_1),
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.txBusy(txBusy_1),
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.txDone(txDone_1),
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.tx(bus_wire)
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);
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initial clk = 1'b0;
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always #SIM_TIMESTEP_FACTOR clk = ~clk;
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initial begin
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integer t;
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$dumpfile(`DUMP_FILE_NAME);
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$dumpvars(0, test);
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#600
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en_1 = 1'b0;
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txStart_1 = 1'b0;
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#600
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en_1 = 1'b1;
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txByte_1 = 8'b01000101;
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$display(" tx data: %8b", txByte_1);
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for (t = 0; t < ENABLED_BAUD_CLOCK_STEPS; t++) begin
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// #1000 x 100ns == 0.1ms == 1 tx clock period (approximately) at 9600 baud
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#1000
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case (t)
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1: begin
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txStart_1 = 1'b1;
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$display("%7.2fms | tx start: %d", $realtime/10000, txStart_1);
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$display("%7.2fms | tx busy: %d, tx done: %d", $realtime/10000, txBusy_1, txDone_1);
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$display("%7.2fms | rx data: %8b", $realtime/10000, rxByte_1);
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end
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4: begin
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txStart_1 = 1'b0;
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$display("%7.2fms | tx start: %d", $realtime/10000, txStart_1);
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end
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13: begin
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// output is ready
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$display("%7.2fms | tx busy: %d, tx done: %d", $realtime/10000, txBusy_1, txDone_1);
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$display("%7.2fms | rx data: %8b", $realtime/10000, rxByte_1);
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end
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endcase
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end
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en_1 = 1'b0;
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#2400
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$finish();
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end
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endmodule

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