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Merge pull request meta-rust#288 from YoeDistro/yoe/mut
Add riscv32/riscv64 support
2 parents 8da0936 + 47de35e commit c72b2dd

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3 files changed

+13
-2
lines changed

3 files changed

+13
-2
lines changed

recipes-devtools/rust/libstd-rs.inc

+4
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,10 @@ RUSTLIB_DEP = ""
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inherit cargo
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DEPENDS_append_libc-musl = " libunwind"
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# rv32 does not have libunwind ported yet
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DEPENDS_remove_riscv32 = "libunwind"
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DEPENDS_remove_riscv64 = "libunwind"
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# Needed so cargo can find libbacktrace
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RUSTFLAGS += "-L ${STAGING_LIBDIR} -C link-arg=-Wl,-soname,libstd.so"
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recipes-devtools/rust/rust-llvm.inc

+1-1
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@@ -19,7 +19,7 @@ LLVM_DIR = "llvm${LLVM_RELEASE}"
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EXTRA_OECMAKE = " \
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-DCMAKE_BUILD_TYPE=Release \
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-DLLVM_TARGETS_TO_BUILD='X86;ARM;AArch64;PowerPC;Mips' \
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-DLLVM_TARGETS_TO_BUILD='ARM;AArch64;Mips;PowerPC;RISCV;X86' \
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-DLLVM_BUILD_DOCS=OFF \
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-DLLVM_ENABLE_TERMINFO=OFF \
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-DLLVM_ENABLE_ZLIB=OFF \

recipes-devtools/rust/rust.inc

+8-1
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,8 @@ def llvm_features_from_tune(d):
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f.append("+a15")
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if 'cortexa17' in feat:
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f.append("+a17")
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if ('riscv64' in feat) or ('riscv32' in feat):
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f.append("+a,+c,+d,+f,+m")
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return f
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# TARGET_CC_ARCH changes from build/cross/target so it'll do the right thing
@@ -291,6 +292,8 @@ def llvm_cpu(d):
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trans['powerpc'] = "powerpc"
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trans['mips64'] = "mips64"
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trans['mips64el'] = "mips64"
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trans['riscv64'] = "generic-rv64"
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trans['riscv32'] = "generic-rv32"
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if target in ["mips", "mipsel"]:
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feat = frozenset(d.getVar('TUNE_FEATURES').split())
@@ -337,6 +340,10 @@ def rust_gen_target(d, thing, wd, features, cpu):
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tspec['env'] = "musl"
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else:
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tspec['env'] = "gnu"
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if "riscv64" in tspec['llvm-target']:
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tspec['llvm-abiname'] = "lp64d"
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if "riscv32" in tspec['llvm-target']:
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tspec['llvm-abiname'] = "ilp32d"
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tspec['vendor'] = "unknown"
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tspec['target-family'] = "unix"
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tspec['linker'] = "{}{}gcc".format(d.getVar('CCACHE'), prefix)

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