@@ -173,11 +173,16 @@ impl CFGR {
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let pllsrcclk = self . hse . unwrap_or ( HSI / 2 ) ;
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let pllmul = self . sysclk . unwrap_or ( pllsrcclk) / pllsrcclk;
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- let pllmul = cmp:: min ( cmp:: max ( pllmul, 1 ) , 16 ) ;
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let ( pllmul_bits, sysclk) = if pllmul == 1 {
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( None , self . hse . unwrap_or ( HSI ) )
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} else {
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+ #[ cfg( not( feature = "connectivity" ) ) ]
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+ let pllmul = cmp:: min ( cmp:: max ( pllmul, 1 ) , 16 ) ;
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+
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+ #[ cfg( feature = "connectivity" ) ]
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+ let pllmul = cmp:: min ( cmp:: max ( pllmul, 4 ) , 9 ) ;
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+
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( Some ( pllmul as u8 - 2 ) , pllsrcclk * pllmul)
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} ;
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@@ -242,7 +247,7 @@ impl CFGR {
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assert ! ( pclk2 <= 72_000_000 ) ;
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// adjust flash wait states
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- #[ cfg( feature = "stm32f103" ) ]
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+ #[ cfg( any ( feature = "stm32f103" , feature = "connectivity" ) ) ]
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unsafe {
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acr. acr ( ) . write ( |w| {
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w. latency ( ) . bits ( if sysclk <= 24_000_000 {
@@ -292,7 +297,8 @@ impl CFGR {
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if let Some ( pllmul_bits) = pllmul_bits {
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// enable PLL and wait for it to be ready
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- rcc. cfgr . modify ( |_, w| {
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+ #[ allow( unused_unsafe) ]
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+ rcc. cfgr . modify ( |_, w| unsafe {
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w. pllmul ( )
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. bits ( pllmul_bits)
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. pllsrc ( )
@@ -305,6 +311,30 @@ impl CFGR {
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}
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// set prescalers and clock source
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+ #[ cfg( feature = "connectivity" ) ]
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+ rcc. cfgr . modify ( |_, w| unsafe {
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+ w. adcpre ( ) . bits ( apre_bits) ;
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+ w. ppre2 ( )
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+ . bits ( ppre2_bits)
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+ . ppre1 ( )
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+ . bits ( ppre1_bits)
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+ . hpre ( )
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+ . bits ( hpre_bits)
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+ . otgfspre ( )
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+ . bit ( usbpre)
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+ . sw ( )
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+ . bits ( if pllmul_bits. is_some ( ) {
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+ // PLL
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+ 0b10
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+ } else if self . hse . is_some ( ) {
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+ // HSE
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+ 0b1
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+ } else {
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+ // HSI
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+ 0b0
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+ } )
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+ } ) ;
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+
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#[ cfg( feature = "stm32f103" ) ]
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rcc. cfgr . modify ( |_, w| unsafe {
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w. adcpre ( ) . bits ( apre_bits) ;
@@ -574,7 +604,7 @@ bus! {
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WWDG => ( APB1 , wwdgen, wwdgrst) ,
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}
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- #[ cfg( feature = "high" ) ]
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+ #[ cfg( any ( feature = "high" , feature = "connectivity" ) ) ]
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bus ! {
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SPI3 => ( APB1 , spi3en, spi3rst) ,
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}
@@ -595,22 +625,19 @@ bus! {
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TIM3 => ( APB1 , tim3en, tim3rst) ,
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}
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- #[ cfg( any( feature = "stm32f100" , feature = "stm32f103" , feature = "stm32f105" , ) ) ]
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+ #[ cfg( any( feature = "stm32f100" , feature = "stm32f103" , feature = "connectivity" ) ) ]
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bus ! {
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TIM1 => ( APB2 , tim1en, tim1rst) ,
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}
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- #[ cfg( any( feature = "stm32f100" , feature = "stm32f105 " , feature = "high" , ) ) ]
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+ #[ cfg( any( feature = "stm32f100" , feature = "high " , feature = "connectivity" ) ) ]
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bus ! {
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TIM6 => ( APB1 , tim6en, tim6rst) ,
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}
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#[ cfg( any(
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- all(
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- feature = "high" ,
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- any( feature = "stm32f101" , feature = "stm32f103" , feature = "stm32f107" , )
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- ) ,
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- any( feature = "stm32f100" , feature = "stm32f105" , )
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+ all( feature = "high" , any( feature = "stm32f101" , feature = "stm32f103" ) ) ,
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+ any( feature = "stm32f100" , feature = "connectivity" )
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) ) ]
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bus ! {
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TIM7 => ( APB1 , tim7en, tim7rst) ,
@@ -628,7 +655,7 @@ bus! {
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TIM4 => ( APB1 , tim4en, tim4rst) ,
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}
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- #[ cfg( feature = "high" ) ]
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+ #[ cfg( any ( feature = "high" , feature = "connectivity" ) ) ]
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bus ! {
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TIM5 => ( APB1 , tim5en, tim5rst) ,
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}
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