@@ -546,7 +546,7 @@ impl<SPI: Instance, const BIDI: bool, W> Spi<SPI, BIDI, W> {
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/// Convert the spi to another mode.
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fn into_mode < const BIDI2 : bool , W2 : FrameSize > ( self ) -> Spi < SPI , BIDI2 , W2 > {
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let mut spi = Spi :: _new ( self . inner . spi , self . pins ) ;
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- spi. enable ( false ) ;
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+ spi. disable ( ) ;
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spi. init ( )
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}
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}
@@ -563,7 +563,7 @@ impl<SPI: Instance, const BIDI: bool, W> SpiSlave<SPI, BIDI, W> {
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/// Convert the spi to another mode.
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fn into_mode < const BIDI2 : bool , W2 : FrameSize > ( self ) -> SpiSlave < SPI , BIDI2 , W2 > {
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let mut spi = SpiSlave :: _new ( self . inner . spi , self . pins ) ;
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- spi. enable ( false ) ;
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+ spi. disable ( ) ;
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spi. init ( )
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}
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}
@@ -642,11 +642,21 @@ impl<SPI: Instance> Inner<SPI> {
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Self { spi }
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}
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- /// Enable/disable spi
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- pub fn enable ( & mut self , enable : bool ) {
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+ /// Enable SPI
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+ pub fn enable ( & mut self ) {
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self . spi . cr1 . modify ( |_, w| {
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// spe: enable the SPI bus
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- w. spe ( ) . bit ( enable)
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+ w. spe ( ) . set_bit ( )
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+ } ) ;
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+ }
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+
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+ /// Disable SPI
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+ pub fn disable ( & mut self ) {
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+ // Wait for !BSY
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+ while self . is_busy ( ) { }
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+ self . spi . cr1 . modify ( |_, w| {
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+ // spe: enable the SPI bus
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+ w. spe ( ) . clear_bit ( )
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} ) ;
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}
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@@ -805,7 +815,10 @@ impl<SPI: Instance> Inner<SPI> {
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// RM SPI::3.5. This is more than twice as fast as the
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// default Write<> implementation (which reads and drops each
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// received value)
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- fn spi_write < const BIDI : bool , W : FrameSize > ( & mut self , words : impl IntoIterator < Item = W > ) -> Result < ( ) , Error > {
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+ fn spi_write < const BIDI : bool , W : FrameSize > (
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+ & mut self ,
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+ words : impl IntoIterator < Item = W > ,
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+ ) -> Result < ( ) , Error > {
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if BIDI {
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self . bidi_output ( ) ;
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}
@@ -824,8 +837,6 @@ impl<SPI: Instance> Inner<SPI> {
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}
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// Wait for final TXE
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while !self . is_tx_empty ( ) { }
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- // Wait for final !BSY
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- while self . is_busy ( ) { }
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if !BIDI {
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// Clear OVR set due to dropped received values
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let _: W = self . read_data_reg ( ) ;
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