listen CTS

Author: burrbull

CHANGELOG.md

@@ -9,7 +9,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Added
 
- - Serial flow control enable
+ - Serial flow control enable [#775]
  - `i2c_scanner` example [#758]
  - Enable `sdio` for stm32f446
  - port LTDC implementation and example from stm32f7xx-hal [#731]
@@ -31,6 +31,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 [#758]: https://github.com/stm32-rs/stm32f4xx-hal/pull/758
 [#725]: https://github.com/stm32-rs/stm32f4xx-hal/pull/725
 
+[#775]: https://github.com/stm32-rs/stm32f4xx-hal/pull/775
+
 ## [v0.21.0] - 2024-05-30
 
 ### Changed

src/serial.rs

@@ -111,6 +111,8 @@ pub enum CFlag {
     TransmissionComplete = 1 << 6,
     /// LIN break detection flag
     LinBreak = 1 << 8,
+    /// Clear to send flag
+    Cts = 1 << 9,
 }
 
 pub mod config;

src/serial/uart_impls.rs

@@ -272,15 +272,22 @@ macro_rules! uartCommon {
 pub trait RBFlowControlImpl {
     fn enable_rts(&self, state: bool);
     fn enable_cts(&self, state: bool);
+    fn listen_cts(&self, state: bool);
 }
 
 impl RBFlowControlImpl for RegisterBlockUsart {
+    #[inline(always)]
     fn enable_rts(&self, state: bool) {
         self.cr3().modify(|_, w| w.rtse().bit(state));
     }
+    #[inline(always)]
     fn enable_cts(&self, state: bool) {
         self.cr3().modify(|_, w| w.ctse().bit(state));
     }
+    #[inline(always)]
+    fn listen_cts(&self, state: bool) {
+        self.cr3().modify(|_, w| w.ctsie().bit(state))
+    }
 }
 
 impl RegisterBlockImpl for RegisterBlockUsart {
@@ -573,6 +580,12 @@ where
     pub fn disable_clear_to_send(&mut self) {
         self.tx.usart.enable_cts(false);
     }
+    pub fn listen_clear_to_send(&mut self) {
+        self.tx.usart.listen_cts(true)
+    }
+    pub fn unlisten_clear_to_send(&mut self) {
+        self.tx.usart.listen_cts(false)
+    }
 }
 
 impl<UART: Instance, WORD> RxISR for Serial<UART, WORD>