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fpistmfpistm
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system(L4) update STM32L4xx HAL Drivers to v1.13.5
Included in STM32CubeL4 FW v1.18.1 Signed-off-by: Frederic Pillon <[email protected]>
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‎system/Drivers/STM32L4xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

+61-19
Original file line numberDiff line numberDiff line change
@@ -275,7 +275,7 @@ extern "C" {
275275
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
276276
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
277277

278-
#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
278+
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
279279
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
280280
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
281281
#endif
@@ -548,6 +548,16 @@ extern "C" {
548548
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
549549
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
550550
#endif /* STM32U5 */
551+
#if defined(STM32U0)
552+
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
553+
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
554+
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
555+
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
556+
#define OB_USER_nBOOT0 OB_USER_NBOOT0
557+
#define OB_USER_nBOOT1 OB_USER_NBOOT1
558+
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
559+
#define OB_nBOOT0_SET OB_NBOOT0_SET
560+
#endif /* STM32U0 */
551561

552562
/**
553563
* @}
@@ -796,6 +806,21 @@ extern "C" {
796806
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
797807
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
798808
#endif /* STM32U5 */
809+
810+
#if defined(STM32WBA)
811+
#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF
812+
#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF
813+
#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF
814+
#define GPIO_AF11_RF_IO1 GPIO_AF11_RF
815+
#define GPIO_AF11_RF_IO2 GPIO_AF11_RF
816+
#define GPIO_AF11_RF_IO3 GPIO_AF11_RF
817+
#define GPIO_AF11_RF_IO4 GPIO_AF11_RF
818+
#define GPIO_AF11_RF_IO5 GPIO_AF11_RF
819+
#define GPIO_AF11_RF_IO6 GPIO_AF11_RF
820+
#define GPIO_AF11_RF_IO7 GPIO_AF11_RF
821+
#define GPIO_AF11_RF_IO8 GPIO_AF11_RF
822+
#define GPIO_AF11_RF_IO9 GPIO_AF11_RF
823+
#endif /* STM32WBA */
799824
/**
800825
* @}
801826
*/
@@ -1239,10 +1264,10 @@ extern "C" {
12391264
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
12401265
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
12411266

1242-
#if defined(STM32H5)
1267+
#if defined(STM32H5) || defined(STM32H7RS)
12431268
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
12441269
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
1245-
#endif /* STM32H5 */
1270+
#endif /* STM32H5 || STM32H7RS */
12461271

12471272
#if defined(STM32WBA)
12481273
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
@@ -1254,10 +1279,10 @@ extern "C" {
12541279
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
12551280
#endif /* STM32WBA */
12561281

1257-
#if defined(STM32H5) || defined(STM32WBA)
1282+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
12581283
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
12591284
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
1260-
#endif /* STM32H5 || STM32WBA */
1285+
#endif /* STM32H5 || STM32WBA || STM32H7RS */
12611286

12621287
#if defined(STM32F7)
12631288
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
@@ -1595,6 +1620,8 @@ extern "C" {
15951620
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
15961621
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
15971622

1623+
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
1624+
15981625
/**
15991626
* @}
16001627
*/
@@ -1805,7 +1832,7 @@ extern "C" {
18051832
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
18061833
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
18071834

1808-
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
1835+
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \
18091836
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
18101837
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
18111838

@@ -1987,12 +2014,12 @@ extern "C" {
19872014
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
19882015
* @{
19892016
*/
1990-
#if defined(STM32H5) || defined(STM32WBA)
2017+
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
19912018
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
19922019
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
19932020
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
19942021
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
1995-
#endif /* STM32H5 || STM32WBA */
2022+
#endif /* STM32H5 || STM32WBA || STM32H7RS */
19962023

19972024
/**
19982025
* @}
@@ -2307,8 +2334,8 @@ extern "C" {
23072334
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
23082335
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
23092336
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
2310-
# endif
2311-
# if defined(STM32F302xE) || defined(STM32F302xC)
2337+
#endif
2338+
#if defined(STM32F302xE) || defined(STM32F302xC)
23122339
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23132340
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23142341
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -2341,8 +2368,8 @@ extern "C" {
23412368
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
23422369
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
23432370
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
2344-
# endif
2345-
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
2371+
#endif
2372+
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
23462373
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
23472374
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
23482375
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
@@ -2399,8 +2426,8 @@ extern "C" {
23992426
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
24002427
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
24012428
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
2402-
# endif
2403-
# if defined(STM32F373xC) ||defined(STM32F378xx)
2429+
#endif
2430+
#if defined(STM32F373xC) ||defined(STM32F378xx)
24042431
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24052432
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
24062433
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
@@ -2417,7 +2444,7 @@ extern "C" {
24172444
__HAL_COMP_COMP2_EXTI_GET_FLAG())
24182445
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
24192446
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
2420-
# endif
2447+
#endif
24212448
#else
24222449
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
24232450
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
@@ -2719,6 +2746,12 @@ extern "C" {
27192746
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
27202747
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
27212748
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
2749+
#if defined(STM32C0)
2750+
#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
2751+
#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
2752+
#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
2753+
#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
2754+
#endif /* STM32C0 */
27222755
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
27232756
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
27242757
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
@@ -3642,8 +3675,12 @@ extern "C" {
36423675
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
36433676
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
36443677

3678+
#if defined(STM32U0)
3679+
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
3680+
#endif
3681+
36453682
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3646-
defined(STM32WL) || defined(STM32C0)
3683+
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
36473684
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
36483685
#else
36493686
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3745,9 +3782,10 @@ extern "C" {
37453782
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
37463783
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
37473784
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
3748-
3785+
#if !defined(STM32U0)
37493786
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
37503787
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
3788+
#endif
37513789

37523790
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
37533791
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
@@ -3893,7 +3931,7 @@ extern "C" {
38933931
*/
38943932
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
38953933
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3896-
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
3934+
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
38973935
#else
38983936
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
38993937
#endif
@@ -3930,7 +3968,8 @@ extern "C" {
39303968

39313969
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
39323970
defined (STM32H7) || \
3933-
defined (STM32L0) || defined (STM32L1)
3971+
defined (STM32L0) || defined (STM32L1) || \
3972+
defined (STM32WB)
39343973
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
39353974
#endif
39363975

@@ -4215,6 +4254,9 @@ extern "C" {
42154254
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
42164255

42174256
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
4257+
4258+
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
4259+
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
42184260
/**
42194261
* @}
42204262
*/

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