Skip to content

Issues: riscv/riscv-isa-manual

Beta
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

220 Open 831 Closed
220 Open 831 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Confusing content of bitmanip extensions
#2019 opened May 15, 2025 by pfusik
VSEPC CSR Implementation
#2018 opened May 14, 2025 by harsha-gunturi
Inconsistency of rs1/r1s
#2012 opened May 8, 2025 by bgrayson-mips
5
addi is supposed to be "constant time", including the immediate value, does this mean mv can't be optimized?
#2000 opened May 4, 2025 by programmerjake
11
Is software expected to do TLB maintenance when going back and forth Pages which are marked as global
#1991 opened Apr 28, 2025 by traviTT
1
Is there any information about RISC-V Matrix Extension can be found ?
#1978 opened Apr 18, 2025 by TJU-PanYizhe
1
Zicsr chapter needs clarification on CSR registers versus CSR instructions/addresses
#1966 opened Apr 10, 2025 by kasanovic
epub format doesn't correctly encode 2^XLEN
#1954 opened Apr 5, 2025 by cryptolovi
1
question regarding dcsr.stepie
#1927 opened Mar 26, 2025 by Wen-Tian-Pineapple
should all the explict CSR read/write operation trigger a micro-arch implemented barrier, or followed a FENCE/Sfence operation
#1912 opened Mar 17, 2025 by rock-ifly
3
Should we add an sfence.vma x0, x0 to synchronize after the PMA setting?
#1909 opened Mar 17, 2025 by rock-ifly
5
How does the privileged / unprivileged spec versioning work?
#1874 opened Feb 26, 2025 by Timmmm
4
Remove the note about software strategies in vfirst.m
#1867 opened Feb 19, 2025 by avakar
1
RVA23 extensions with missing or incompete version numbers
#1866 opened Feb 18, 2025 by tariqkurd-repo
3
clarify vector extension documentation
#1863 opened Feb 18, 2025 by tariqkurd-repo
ch6-sepmp -- Whether should we add a sfence.vma after configuring the epmp extension by setting the mseccfg.mmwp/mml bits?
#1859 opened Feb 14, 2025 by rock-ifly
6
Integrate E-Trace Encapsulation Integration Pending Integration
#1858 opened Feb 13, 2025 by rpsene
3
Integrate Capacity and Bandwidth Controller QoS Register Interface Pending Integration
#1857 opened Feb 13, 2025 by rpsene
1
Integrate AIA Pending Integration
#1856 opened Feb 13, 2025 by rpsene
2
Changes to support building Priv and Unpriv manuals as adoc "parts" in a larger adoc "book"
#1826 opened Jan 26, 2025 by james-ball-qualcomm
@wmat @james-ball-qualcomm
4
Smepmp extension chapter needs a rewrite to make it normative
#1818 opened Jan 21, 2025 by radimkrcmar
7
What does "inlined" mean?
#1814 opened Jan 17, 2025 by kersten1
18
Replace long form id syntax with short form on antora-refactor branch
#1813 opened Jan 17, 2025 by wmat
@wmat
Use unified spec describe CSR registers
#1809 opened Jan 16, 2025 by trdthg
3
Questions about constraints on misa.V and xstatus.VS
#1802 opened Jan 15, 2025 by Vivvvvvvv
3
ProTip! Updated in the last three days: updated:>2025-05-12.